Digital circuit devices typically include flip-flops, latches, or other storage circuits controlled by a clock signal. These devices receive both a data signal and a clock signal. In order to properly store a data signal, the data signal must be present on the data input terminal close to or during the active clock transition.
Within an IC device, the proper timing can be reliably achieved by carefully designing the clock distribution network. If the worst case clock skew (time spread over which a clock edge arrives at the various flip-flops on the chip) is less than the sum of the clock-to-output delay (time from when a clock edge is applied to the clock terminal of a flip-flop and the data appear on the flip-flop output terminal) plus the minimum interconnect delay, there is never a problem that a data signal will be removed from a flip-flop input terminal before the clock signal has caused the data to be captured.
However, signals applied from external sources to pins of the IC device must be carefully timed so that the IC device will respond correctly. Practically, a time window during which valid data must be present on the data input terminal is specified in order to guarantee predictable performance over the full range of operating conditions and manufacturing tolerances. This time window is discussed at page 13-45 of "The Programmable Logic Data Book" published in September, 1996 by Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, assignee of the present invention.
This time window often extends on both sides of a clock edge. The time before the clock edge during which data are required to be present and stable is called "set-up time" and the time after the clock edge during which data are required to be present and stable is called "hold time". Since data applied from an external pin to a flip-flop data input terminal will stabilize at the data source some time after a certain clock edge (clock-to-out time), and data must be available at the flip-flop data input terminal before the next clock edge (set-up time), the maximum clock frequency is limited by the sum of clock-to-out time and set-up time; therefore, it is desirable that set-up time be as short as possible.
An on-chip clock signal is often distributed globally from a single input pin to an entire chip or a large part of a chip. In large integrated circuit devices having global clock signals there is a clock distribution delay, which is the time difference between when a global clock signal is applied to the external pin and when the global clock signal arrives at a last point in the IC device. Thus, it is necessary to account for the clock distribution delay.
Large clock distribution delay can create large hold time requirements for signals going to points distant from the clock source (the time an externally applied data signal is required to remain stable after an externally applied clock edge appears), since data must be present at the data input terminal of a particular flip-flop when the clock signal switches at the clock input terminal of that flip-flop. Failing to meet a hold time requirement can cause data errors, and in particular can cause a race condition. A race condition occurs when a data source is not guaranteed to maintain a first data signal beyond a time when a clock edge arrives at a flip-flop receiving the data signal. Erroneously, the flip-flop may receive a second data signal and miss the first data signal. This race condition is usually a fatal system error. Therefore, chips are usually designed not to have hold time requirements.
Xilinx, Inc., assignee of the present invention, has addressed the clock distribution delay and potential hold-time problems by adding a deliberate delay to every data input signal coming from an external pin. In some FPGAs, this added delay is fixed and always present; in other FPGAs, the delay is optional, and its value is tailored to the clock distribution delay; generally, delay is larger for larger devices since larger devices tend to have larger clock distribution delay. As a result of this added delay, no Xilinx FPGA has a hold time requirement, but the set-up time is significant. Since the longest set-up time limits the operating speed or maximum clock rate of a system, it is desirable to minimize the set-up time, but without requiring a hold time.